1. Field of the Invention
The present invention relates to rendering processing apparatuses and methods for rendering data used to display images, and more particularly, to a rendering processing apparatus and method efficiently performing buffer control of image data for displaying an image on a display unit based on the image data.
2. Description of the Background Art
In a rendering processing system of three-dimensional graphics, for example, a series of rendering processes are performed as follows: image data are generated for display of an image; the generated image data are stored in a memory, such as a frame buffer; and the image is displayed on a display unit, such as a cathode ray tube (CRT), based on the image data stored in the memory such as the frame buffer. In particular, to smoothly display images, various approaches have been taken to improve buffering control for temporarily storing image data in a frame buffer or the like, in order to efficiently transfer the image data to a display unit according to a video refresh period. One of such buffering control is a double buffering control as disclosed, for example, in Japanese Patent Laying-Open No. 6-19675.
A rendering processing system performing such double buffer control includes: a rendering engine for generating image data; and two frame memories called an A plane and a B plane each storing one-frame-basis image data. While the one-frame-basis image data stored in the A plane are being output to a display unit, the rendering engine writes image data for a next frame into the B plane. When the output of the one-frame image data stored in the A plane is completed, the image data for the next frame stored in the B plane are output to the display unit. During the transfer of the image data from the B plane to the display unit, the rendering engine writes image data for a next frame into the A plane. Thus, the two frame memories, A plane and B plane, are controlled to function alternately as a rendering plane for having the rendering data written thereinto and a displaying plane for outputting the image data to the display unit.
In the three-dimensional graphics processing, the rendering data stored in each of the two memories is comprised of a plurality of pixel data corresponding to a plurality of pixels included in one frame. Each of the pixel data includes three-color information R, G, B representing red, green and blue of the pixel, respectively, and xcex1 value information representing transparency of the pixel.
Normally, the rendering engine and the two frame memories are formed of separate semiconductor chips. Some approaches have been taken to increase the rendering speed, which approaches include: to widen a bus width connecting the rendering engine and each frame memory; and to utilize a high-speed memory as the frame memory. However, the widening of the bus width is restricted due to the limited number of input/output pin terminals of the memory and to the increase of the charge/discharge current. The speeding-up of the memory is also limited.
Based on the above, it has been considered to incorporate a frame memory in a rendering engine formed of one chip. However, arranging two frame memories each storing a large amount of data on the same semiconductor chip increases both the chip area and the cost.
An object of the present invention is to provide a rendering processing apparatus having a buffering frame memory reduced in storage capacity.
Another object of the present invention is to provide a rendering processing apparatus performing buffering control that can reduce storage capacity required for a memory.
Further object of the present invention is to provide a method of controlling a buffering on pixel data to reduce a required memory storage capacity in rendering processing.
The rendering processing apparatus according to the present invention includes: a rendering operation circuit for performing an operation for generating a plurality of pixel data corresponding to a plurality of pixels constituting one display screen; a first memory for storing the plurality of pixel data generated by the rendering operation circuit; and a transfer circuit for transferring pixel data corresponding to each of the pixel data with prescribed information removed therefrom to a second memory for storage. The second memory outputs the stored data for display by a display unit on a display screen thereof.
The rendering processing apparatus according to another aspect of the present invention includes: rendering operation circuitry performing an operation for generating a plurality of pixel data corresponding to a plurality of pixels constituting a screen; and a first memory for storing the plurality of plurality of received from the rendering circuitry; and a transfer circuit connected to the first memory for obtaining transfer data from the plurality of pixel data excluding prescribed data for transference to a second memory.
The pixel data includes three-color information of red, green and blue, and alpha value information representing transparency of a corresponding pixel. The prescribed data includes at least the alpha value information of each of the pixel data.
The rendering image method according to further aspect of the present invention includes the steps of: generating a plurality of first pixel data corresponding to a plurality of pixels constituting a screen; storing the plurality of first pixel data in a first memory; transfer first transfer data to a second memory through a data bus; storing the first transfer data in the second memory; and transfer the first transfer data from the second memory to a display unit for displaying an image.
First pixel data each include three-color information of red, green and blue, and alpha value information representing transparency of a corresponding pixel. First transfer data is obtained from the plurality of excluding at least the alpha value information of each first pixel data.
Each of the plurality of pixel data stored in the first memory includes three-color information representing red, green and blue of the pixel, and a value information representing transparency of the pixel. The prescribed information removed in the transfer circuit includes the xcex1 value information.
The second memory is not required to store the xcex1 value information at least, and therefore, it is possible to reduce the data amount to be stored in the second memory. In addition, the data amount to be transferred to the second memory is small, which leads to the reduction in the time required for the data transfer, and thus, high-speed data transfer can be implemented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.